Alchip Technologies Announces Plans to Support 3DFabric(TM) Alliance

Taipei, Taiwan, Feb. 01, 2023 (GLOBE NEWSWIRE) — Alchip Technologies is adding teeth to its role as a founding member of TSMC’s 3DFabric™ Alliance by advancing its 3nm process technology and advanced packaging capabilities.

The company supports the foundry initiative, announced in late October, as a market engine that will deliver Alchip’s most advanced high-performance computing ASIC technology to leading consumer applications.

TSMC’s 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unleash customer innovation in a system-level approach. It consists of TSMC’s front-end technologies or TSMC-SoIC™ (System on Integrated Chips), specialized fabs for 3D stacked die assembly and testing, and TSMC 3DFabric’s back-end technologies include CoWoS and InFO family of packaging technologies.

The TSMC 3DFabric Alliance is the latest addition to TSMC’s Open Innovation Platform® (OIP). New alliance partners have early access to TSMC’s 3DFabric technologies, allowing them to develop and optimize their solutions alongside TSMC. This gives customers early access to EDA, IP, memory, outsourced semiconductor assembly and test (OSAT), substrate and test.

“As a high-performance computing ASIC leader, Alchip’s participation in the TSMC 3DFabric Alliance is imperative,” said Johnny Shen, president and CEO of Alchip Technologies. “This new initiative solidifies TSMC’s semiconductor leadership by providing strategic opportunities for leading, high-performance ASIC companies to extend their cutting-edge packaging capabilities to customers with innovative technologies.”

Alchip uses a 3nm customer ASIC design and recorded its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce a comprehensive design readiness and manufacturing ecosystem targeting TSMC’s latest N3E technology.

On the advanced packaging front, Alchip is fine-tuning its industry-leading chip-on-safe-substrate (CoWoS®) packaging capability. CoWoS improves overall chip interconnect density and performance, and is critical to nearly every high-performance computing (HPC) ASIC.

CoWoS is a 2.5D multi-chip wafer-level packaging technology that features a side-by-side die on a silicon interposer. The micro-bumps connect individual chips with a silicon spacer, forming a chip on a wafer. The packaging is completed by bonding to the packaging substrate.

CoWoS chiplet kits include a high-performance system-on-chip (SoC) and a high-performance memory block (HBM3 or HBM2E). Alchip’s CoWoS service covers all types of CoWoS packages such as CoWoS-S, CoWoS-R and CoWoS-L.

For more information about Alchip, visit

About Alchip

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global supplier of silicon and design and manufacturing services to system companies developing complex and high-volume ASICs and SoCs. The company provides faster time-to-market and cost-effective SoC design solutions at mainstream and advanced, including 7nm, 6nm, 5nm and 4nm processes. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D package services, CoWoS/chiplet design and manufacturing expertise. Customers include world leaders in AI, HPC/supercomputing, mobile phones, entertainment devices, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661), is a TSMC Certified Value Chain Aggregator, and is a founding member of the new TSMC 3DFabric Alliance®.

  • Examples of CoWoS Chipsets

Charles Byers
Alchip Technologies
+ (408)-310-9244
[email protected]

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